A package-processed stacked memory is attracting attention as a method of reducing costs and enabling high integration in relation to a non-volatile semiconductor memory device. A package-processed stacked memory is manufactured by firstly providing alternate laminated layers of an insulating film and an electrode film on a semiconductor substrate to form a stacked body. Then a through-hole is formed in the stacked body with a lithography method, a blocking layer, a charge storage layer, and a tunneling layer are sequentially formed on an inner surface of the through-hole, and a silicon pillar is buried into the through-hole. In this stacked memory, a memory transistor is formed in the intersection of the electrode film and the silicon pillar, to form a memory cell. Since the memory cells can be stacked in a three-dimensional configuration in this type of stacked memory, high integration and cost reduction in relation to a memory device is enabled (for example refer to JP-A No. 2009-146954 (Kokai)). However demand for further increases in integration is expected in relation to this type of stacked memory.